1. Field of the Invention
This invention relates to digital-to-analog converters, and more particularly to an integrated latchable bit current switch circuit having a capacitance reduced settling time.
2. Prior Art
Digital-to-analog converters typically have a plurality of differential transistor pairs functioning as switches. Digital input signals representative of a binary number determine the on-off state of each switch wherein the on state of each switch supplies a binary scaled bit current to a summing bus to form an analog signal corresponding to the digital input signal.
One such type of switch, the Craven cell, is described in U.S. Pat. No. 3,961,326. The Craven cell comprises a first differential transistor pair which are biased by an input signal and a reference voltage, and a second differential pair which switch the bit current between the output bus and ground. However, in the Craven cell, a rapid change in the input level is coupled through the base-collector capacitance of the input transistor of the first differential pair and affects the voltage at the base of one of the transistors in the second differential pair. Thus, the voltages at the bases of the second differential pair are not precisely differential voltages. This causes a glitch at the emitters of the second differential pair which, especially in the case of low bit currents, may take a considerable amount of time to settle out.
Another known switch that substantially eliminates the glitches inherent in the Craven cell is described in U.S. Pat. No. 4,295,063, wherein a first differential transistor pair is biased by a digital input signal and a reference voltage, a second differential transistor pair directs a bit current onto a summing bus, and a third differential transistor pair has an input coupled to the first pair and an output coupled to the second pair for reducing any overshoot in the magnitude of the output caused by fast transitions of the input signals.
Another known switch, wherein the output may be latched, comprises a first differential transistor pair biased by a digital input signal and a reference voltage, a second differential transistor pair that are cross-coupled and are responsive to the output of the first pair, a third differential transistor pair responsive to the output of the first and second pair for directing an output current onto a summing bus, and a fourth differential transistor pair responsive to toggle and latch signals for enabling either the first or second pair. However, parasitic feedback caused by the junction capacitance in the third and fourth pair due to the fast transitions of the digital input signal and toggle and latch signals creates an overshooting or glitches in the output signal on the summing bus.
Thus, what is needed is a latchable bit switch that reduces parasitic feedback or glitches in the output caused by the junction capacitance of switching devices, thereby reducing the settling time or ringing of output.